1. Field of the Invention
This invention relates generally to dynamic memory devices, and, more specifically, to a dynamic memory device adapted to be accessed with an adjustable burst length, column address strobe (CAS) latency, and/or write latency.
2. Description of the Related Art
Generally, there are at least two types of data transfers to and from memory. A first type includes a data transfer for a main client that requires large amounts of data to be transferred to and from the memory. A second type of data transfer is for a peripheral client that typically requires small amounts of data to be transferred to and from the memory.
To allow greater flexibility for data transfers, many of today's dynamic memory devices, such as Synchronous RAM (SDRAM), double data rate SDRAM devices (DDR SDRAM), Rambus™ DRAM (RDRAM) and the like, are usually designed to operate at various latency levels and burst lengths. For example, a semiconductor memory device may perform a latency and burst operation with latency 1, 2, and 3, and variable operation modes of burst length 1, 2, 4 and 8. The latency level and the burst length for a given mode of operation of the semiconductor memory device are commonly defined by a programmable mode register.
CAS latency is the delay that may be measured in clock cycles, between the presentation of a READ command and the availability of the first bit of the output data. For example, if latency is set at 3, data is output from the memory 3 clock cycles after a read command or signal is applied to the memory.
The term “burst length” refers to a number of column locations that can be accessed from the memory in which the read and write accesses to memory are burst oriented. In a burst operation, a column address is provided after a row address, and data from continuous column addresses thereafter is output at high speed in synchronization with a clock signal. For example, if burst length is set at eight (8), a semiconductor memory device outputs, for example, eight (8) bits of data in synchronization with the clock signal based on a starting column address. Typically, if a starting column address is provided from an external source, the next seven (7) column addresses are generated internally by a column address generation circuit.
While a semiconductor memory device may be capable of supporting multiple modes of operation (i.e., different latency levels and/or burst lengths), as a general matter, the operation mode of the memory device cannot be altered without reprogramming its mode register. Changing the operation mode of the memory device, however, may be a time consuming process, as the reprogramming must be loaded (or reloaded) when all memory banks are idle and no bursts are in progress. Furthermore, the memory controller must wait a specified amount of time before initiating a subsequent operation after the mode register has been programmed or reprogrammed to a desired state. Additionally, in conventional memory devices, the operation mode of the memory device cannot be altered substantially concurrently with an access command (e.g., read command and write command). This may result in power wastage, as multiple commands may be needed to change the operation mode of the memory device and to access the contents of the memory device.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.